FP: Open Source RFIC Design
(suitable for HW/FP/MA; scope and depth will be adapted to ECTS and prior knowledge)
Description
We will build an end-to-end RFIC design flow (schematic → layout → EM → co-simulation) both with open-source tools and in commercial environments, and correlate the results.The work includes IC design (schematic, layout, verification) in Cadence/ADS and Ansys HFSS/CST, as well as with open-source tools (Qucs-S/Ngspice/Xyce, KLayout/gdsfactory, openEMS, scikit-rf).
Research Questions
- How large are the discrepancies between the open-source flow and Cadence/ADS/HFSS/CST for S-parameters, NF, P1dB, IP3, and phase noise, and which causes dominate (models, ports, meshing, de-embedding)
- How can the open-source flow be simplified and at which knobs can it be improved (netlisting, EM settings)?
- How can thermal simulation results be obtained with open-source tools and then fed back into the design flow?
- How can thermals be integrated so that the temperature distribution is fed back into the flow and the performance impact of heating (e.g., Gain/NF/IL/PAE/phase noise) becomes visible at the system level?
Research Goals
- Set up and document the open-source flow (Qucs-S/Ngspice/Xyce, KLayout/gdsfactory, openEMS, scikit-rf)
- Benchmark against Cadence/ADS/HFSS/CST.
- Deviation analysis: identify and minimize causes (models, port/de-embedding, numerics, meshing, PEX/EM).
- Automation: Python pipelines for sweeps, analysis, plots, and reports.
- Thermal/Electro-thermal: derive power density from circuits, thermally simulate selected sub-structures (e.g., Elmer FEM), and back-annotate the resulting temperatures into circuit/EM simulation (temperature parameters, R/μ/Q dependencies) to assess the system-level performance impact.
Topics
- System & Specification
- Target metrics/corner plan; defined testbenches (Open Source ↔ Cadence)
- Circuit Simulation
- Qucs-S/Ngspice/Xyce: AC/S-parameters/noise/transient; optional HB in Xyce.
- Layout & EM
- KLayout/gdsfactory (parametric PCells), openEMS (FDTD), de-embedding, Touchstone export.
- Thermal & Electro-Thermal Co-Simulation
- Power map from circuit simulation (DC/AC/losses).
- 2D/3D heat conduction (steady-state, optional transient) incl. package/BCs.
- Temperature back-annotation into circuit/EM (device temperature, R/μ/Q models).
- Iterative loop to convergence; evaluate performance impact.
Skills
(Not all are required; two profiles are possible. We tailor the tasks accordingly.)
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Programmierung/EDA
- Solid Python skills (NumPy, Pandas, SciPy; ideally scikit-rf).
- Interest in new tools.
- Basics of Cadence/ADS/HFSS/CST-Basics are a plus.
- Linux fundamentals, reproducible workflows.
RF-Design
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Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.
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Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).
