(suitable for HW/FP/MA; scope and depth will be adapted to ECTS and prior knowledge)
Description
We will build an end-to-end RFIC and RF packaging design flow
(schematic → layout → EM → circuit/EM co-simulation) using both open-source tools and commercial environments, and systematically correlate the results.
The focus of this work is RF packaging and chip–package–PCB transitions, including bondwires, bond pads, package interconnects, and RF transitions to PCB or antennas.
The work includes:
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RFIC and package-aware circuit design (schematic, layout, verification)
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Full-wave EM simulation of packaging structures
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Circuit–EM co-simulation and de-embedding
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Benchmarking open-source tools against Cadence / ADS / HFSS / CST
Research Question
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How large are the discrepancies between open-source and commercial tools for:
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S-parameters
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Gain, NF, P1dB, IP3
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Phase and group delay
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Which effects dominate these discrepancies:
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Packaging parasitics (bondwires, pads, transitions)
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Port definitions and de-embedding
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EM meshing and numerical settings
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Model and layout abstractions
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How accurately can chip–package–PCB transitions be modeled with open-source EM solvers?
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How can the open-source RF packaging flow be simplified and improved:
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Netlisting and co-simulation interfaces
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EM setup, boundary conditions, and ports
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Automation and reproducibility
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Research Goals
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Develop parametric packaging models:
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Bondwires, pad stacks, package transitions
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Automation:
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Python pipelines for parameter sweeps, EM simulations, post-processing and packaging simulation
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Skills
- Overall grade better than 2.0
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Programmierung/EDA
- Solid Python skills
- Interest in new tools.
- Basics of Cadence/ADS/HFSS/CST-Basics are a plus.
- Linux fundamentals, reproducible workflows.
RF-Design
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Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.
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Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).