The Open Electronics Lab invites students to gain first-hand experience in the design and fabrication of digital integrated circuits in their spare time.
Thanks to the Tiny Tapeout platform, it is now possible to realize personal digital designs using open-source PDKs and tools, all the way through to physical fabrication.
As part of this research internship, a simple digital circuit (e.g., an FSM or similar design) will be implemented from logical specification to layout and submitted for fabrication. The project will make use of the established open-source toolchain available at the chair.
In addition, the entire design workflow for the Tiny Tapeout platform will be documented and evaluated in terms of usability and reproducibility.
Research Questions
- What challenges arise when implementing digital designs using open-source EDA tools?
- How reliable are the synthesis, place-and-route, and verification steps compared to industrial tools?
- Which design flows are best suited for teaching and prototyping small digital systems?
- Where can the Tiny Tapeout workflow be automated or optimized?
Objectives
- Documentation of a complete digital design workflow for a Tiny Tapeout MPW run
- Design, simulation, synthesis, and layout of a simple digital circuit
- Evaluation of open-source tools for educational and research applications
Work Packages
- System & Specification
- Definition of functionality, interfaces, and design metrics
- RTL Design & Verification
- Design in Verilog/SystemVerilog
- Functional simulation using Icarus Verilog, Verilator, or GTKWave
- Synthesis & Implementation
- Logic synthesis with Yosys, place-and-route with OpenLane
- Signoff checks (DRC/LVS) and GDS generation
- Documentation & Automation
- Script-based workflow (Makefile/Python), reproducibility, and CI integration
Your Background
(Not all criteria are mandatory.)
- General:
- Strong academic performance (overall grade better than 2.0)
- Interest in digital design and open-source EDA tools
- Field of study: Electrical Engineering, Computer Science, or related
- Programming & EDA:
- Solid knowledge of Verilog or VHDL
- Experience with Python for automation and testbenching
- Basic experience with Linux and reproducible workflows
- Familiarity with OpenLane, Yosys, Magic, or KLayout is an advantage
- Digital Design:
- Understanding of digital design fundamentals (logic, FSMs, clocking, pipelines)
- Attendance of courses or labs such as VHDL or Digital ASIC Design Lab is beneficial
- Practical Skills & Motivation:
- Enthusiasm for experimenting with new tools
- Interest in IC design, digital verification, and open-source design flows