Research Questions<\/h3>\n\n- How large are the discrepancies between the open-source flow and Cadence\/ADS\/HFSS\/CST for S-parameters, NF, P1dB, IP3,<\/strong> and phase noise<\/strong>, and which causes dominate (models, ports, meshing, de-embedding)<\/li>\n
- How can the open-source flow be simplified<\/strong> and at which knobs can it be improved<\/strong> (netlisting, EM settings)?<\/li>\n
- How can thermal simulation results<\/strong> be obtained with open-source tools and then fed back<\/strong> into the design flow?<\/li>\n
- How can thermals<\/strong> be integrated so that the temperature distribution is fed back into the flow and the performance impact of heating (e.g., Gain\/NF\/IL\/PAE\/phase noise) becomes visible at the system level?<\/li>\n<\/ul>\n
Research Goals<\/h3>\n\n- Set up and document the open-source flow<\/strong> (Qucs-S\/Ngspice\/Xyce, KLayout\/gdsfactory, openEMS, scikit-rf)<\/li>\n
- Benchmark against Cadence\/ADS\/HFSS\/CST<\/strong>.<\/li>\n
- Deviation analysis:<\/strong> identify and minimize causes (models, port\/de-embedding, numerics, meshing, PEX\/EM).<\/li>\n
- Automation:<\/strong> Python pipelines for sweeps, analysis, plots, and reports.<\/li>\n
- Thermal\/Electro-thermal:<\/strong> derive power density from circuits, thermally simulate selected sub-structures (e.g., Elmer FEM), and back-annotate the resulting temperatures into circuit\/EM simulation (temperature parameters, R\/\u03bc\/Q<\/strong> dependencies) to assess the system-level performance impact.<\/li>\n<\/ul>\n
Topics<\/strong><\/h3>\n\n- System & Specification<\/strong>\n
\n- Target metrics\/corner plan; defined testbenches (Open Source \u2194 Cadence<\/strong>)<\/li>\n<\/ul>\n<\/li>\n
- Circuit Simulation<\/strong>\n
\n- Qucs-S\/Ngspice\/Xyce: AC\/S-parameters\/noise\/transient; optional HB in Xyce.<\/li>\n<\/ul>\n<\/li>\n
- Layout & EM<\/strong>\n
\n- KLayout\/gdsfactory (parametric PCells), openEMS (FDTD), de-embedding, Touchstone export.<\/li>\n<\/ul>\n<\/li>\n
- Thermal & Electro-Thermal Co-Simulation<\/strong>\n
\n- Power map from circuit simulation (DC\/AC\/losses).<\/li>\n
- 2D\/3D heat conduction (steady-state, optional transient) incl. package\/BCs.<\/li>\n
- Temperature back-annotation into circuit\/EM (device temperature, R\/\u03bc\/Q models).<\/li>\n
- Iterative loop to convergence; evaluate performance impact.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
Skills<\/strong><\/h3>\n(Not all are required; two profiles are possible. We tailor the tasks accordingly.)<\/p>\n
\n- Overall grade better than 2.0<\/li>\n
- \n
Programmierung\/EDA<\/span><\/p>\n\n- Solid Python skills (NumPy, Pandas, SciPy; ideally scikit-rf).<\/li>\n
- Interest in new tools.<\/span><\/li>\n
- Basics of Cadence\/ADS\/HFSS\/CST-Basics are a plus.<\/span><\/li>\n
- Linux fundamentals, reproducible workflows.<\/span><\/li>\n<\/ul>\n
RF-Design<\/span><\/p>\n\n- \n
Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.<\/p>\n<\/li>\n
- \n
Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
\u00a0<\/p>\n
Anfrage senden<\/span><\/a><\/p>\n\n\n\n\n\n\nContact<\/h3>\n\n\n\r\n \r\n \r\n \r\n \r\n ![\"GS\"](\"https:\/\/www.lites.tf.fau.de\/files\/2025\/02\/Image.jpg\")
<\/figure> <\/div>\r\n \r\n Gianluca<\/span> Simone<\/span><\/span><\/span><\/a><\/h1>Chair of Smart Electronics and Systems<\/span><\/p>Research associates<\/p> \r\n <\/header>\r\n
\r\n Address<\/h2>Cauerstra\u00dfe 7-9<\/span> 91058<\/span> Erlangen<\/span><\/span><\/address><\/div><\/div>Contact<\/h2>- Email: <\/span>gianluca.simone@fau.de<\/a><\/span><\/li><\/ul><\/div>
Research Goals<\/h3>\n\n- Set up and document the open-source flow<\/strong> (Qucs-S\/Ngspice\/Xyce, KLayout\/gdsfactory, openEMS, scikit-rf)<\/li>\n
- Benchmark against Cadence\/ADS\/HFSS\/CST<\/strong>.<\/li>\n
- Deviation analysis:<\/strong> identify and minimize causes (models, port\/de-embedding, numerics, meshing, PEX\/EM).<\/li>\n
- Automation:<\/strong> Python pipelines for sweeps, analysis, plots, and reports.<\/li>\n
- Thermal\/Electro-thermal:<\/strong> derive power density from circuits, thermally simulate selected sub-structures (e.g., Elmer FEM), and back-annotate the resulting temperatures into circuit\/EM simulation (temperature parameters, R\/\u03bc\/Q<\/strong> dependencies) to assess the system-level performance impact.<\/li>\n<\/ul>\n
Topics<\/strong><\/h3>\n\n- System & Specification<\/strong>\n
\n- Target metrics\/corner plan; defined testbenches (Open Source \u2194 Cadence<\/strong>)<\/li>\n<\/ul>\n<\/li>\n
- Circuit Simulation<\/strong>\n
\n- Qucs-S\/Ngspice\/Xyce: AC\/S-parameters\/noise\/transient; optional HB in Xyce.<\/li>\n<\/ul>\n<\/li>\n
- Layout & EM<\/strong>\n
\n- KLayout\/gdsfactory (parametric PCells), openEMS (FDTD), de-embedding, Touchstone export.<\/li>\n<\/ul>\n<\/li>\n
- Thermal & Electro-Thermal Co-Simulation<\/strong>\n
\n- Power map from circuit simulation (DC\/AC\/losses).<\/li>\n
- 2D\/3D heat conduction (steady-state, optional transient) incl. package\/BCs.<\/li>\n
- Temperature back-annotation into circuit\/EM (device temperature, R\/\u03bc\/Q models).<\/li>\n
- Iterative loop to convergence; evaluate performance impact.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
Skills<\/strong><\/h3>\n(Not all are required; two profiles are possible. We tailor the tasks accordingly.)<\/p>\n
\n- Overall grade better than 2.0<\/li>\n
- \n
Programmierung\/EDA<\/span><\/p>\n\n- Solid Python skills (NumPy, Pandas, SciPy; ideally scikit-rf).<\/li>\n
- Interest in new tools.<\/span><\/li>\n
- Basics of Cadence\/ADS\/HFSS\/CST-Basics are a plus.<\/span><\/li>\n
- Linux fundamentals, reproducible workflows.<\/span><\/li>\n<\/ul>\n
RF-Design<\/span><\/p>\n\n- \n
Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.<\/p>\n<\/li>\n
- \n
Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
\u00a0<\/p>\n
Anfrage senden<\/span><\/a><\/p>\n\n\n\n\n\n\nContact<\/h3>\n\n\n\r\n \r\n \r\n \r\n \r\n <\/figure> <\/div>\r\n \r\n Gianluca<\/span> Simone<\/span><\/span><\/span><\/a><\/h1>Chair of Smart Electronics and Systems<\/span><\/p>Research associates<\/p> \r\n <\/header>\r\n
\r\n Address<\/h2>Cauerstra\u00dfe 7-9<\/span> 91058<\/span> Erlangen<\/span><\/span><\/address><\/div><\/div>Contact<\/h2>- Email: <\/span>gianluca.simone@fau.de<\/a><\/span><\/li><\/ul><\/div>
Topics<\/strong><\/h3>\n\n- System & Specification<\/strong>\n
\n- Target metrics\/corner plan; defined testbenches (Open Source \u2194 Cadence<\/strong>)<\/li>\n<\/ul>\n<\/li>\n
- Circuit Simulation<\/strong>\n
\n- Qucs-S\/Ngspice\/Xyce: AC\/S-parameters\/noise\/transient; optional HB in Xyce.<\/li>\n<\/ul>\n<\/li>\n
- Layout & EM<\/strong>\n
\n- KLayout\/gdsfactory (parametric PCells), openEMS (FDTD), de-embedding, Touchstone export.<\/li>\n<\/ul>\n<\/li>\n
- Thermal & Electro-Thermal Co-Simulation<\/strong>\n
\n- Power map from circuit simulation (DC\/AC\/losses).<\/li>\n
- 2D\/3D heat conduction (steady-state, optional transient) incl. package\/BCs.<\/li>\n
- Temperature back-annotation into circuit\/EM (device temperature, R\/\u03bc\/Q models).<\/li>\n
- Iterative loop to convergence; evaluate performance impact.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
Skills<\/strong><\/h3>\n(Not all are required; two profiles are possible. We tailor the tasks accordingly.)<\/p>\n
\n- Overall grade better than 2.0<\/li>\n
- \n
Programmierung\/EDA<\/span><\/p>\n\n- Solid Python skills (NumPy, Pandas, SciPy; ideally scikit-rf).<\/li>\n
- Interest in new tools.<\/span><\/li>\n
- Basics of Cadence\/ADS\/HFSS\/CST-Basics are a plus.<\/span><\/li>\n
- Linux fundamentals, reproducible workflows.<\/span><\/li>\n<\/ul>\n
RF-Design<\/span><\/p>\n\n- \n
Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.<\/p>\n<\/li>\n
- \n
Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
\u00a0<\/p>\n
Anfrage senden<\/span><\/a><\/p>\n\n\n\n\n\n\nContact<\/h3>\n\n\n\r\n \r\n \r\n \r\n \r\n <\/figure> <\/div>\r\n \r\n Gianluca<\/span> Simone<\/span><\/span><\/span><\/a><\/h1>Chair of Smart Electronics and Systems<\/span><\/p>Research associates<\/p> \r\n <\/header>\r\n
\r\n Address<\/h2>Cauerstra\u00dfe 7-9<\/span> 91058<\/span> Erlangen<\/span><\/span><\/address><\/div><\/div>Contact<\/h2>- Email: <\/span>gianluca.simone@fau.de<\/a><\/span><\/li><\/ul><\/div>
- \n
- Target metrics\/corner plan; defined testbenches (Open Source \u2194 Cadence<\/strong>)<\/li>\n<\/ul>\n<\/li>\n
- Circuit Simulation<\/strong>\n
- \n
- Qucs-S\/Ngspice\/Xyce: AC\/S-parameters\/noise\/transient; optional HB in Xyce.<\/li>\n<\/ul>\n<\/li>\n
- Layout & EM<\/strong>\n
- \n
- KLayout\/gdsfactory (parametric PCells), openEMS (FDTD), de-embedding, Touchstone export.<\/li>\n<\/ul>\n<\/li>\n
- Thermal & Electro-Thermal Co-Simulation<\/strong>\n
- \n
- Power map from circuit simulation (DC\/AC\/losses).<\/li>\n
- 2D\/3D heat conduction (steady-state, optional transient) incl. package\/BCs.<\/li>\n
- Temperature back-annotation into circuit\/EM (device temperature, R\/\u03bc\/Q models).<\/li>\n
- Iterative loop to convergence; evaluate performance impact.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
Skills<\/strong><\/h3>\n
(Not all are required; two profiles are possible. We tailor the tasks accordingly.)<\/p>\n
- \n
- Overall grade better than 2.0<\/li>\n
- \n
Programmierung\/EDA<\/span><\/p>\n
- \n
- Solid Python skills (NumPy, Pandas, SciPy; ideally scikit-rf).<\/li>\n
- Interest in new tools.<\/span><\/li>\n
- Basics of Cadence\/ADS\/HFSS\/CST-Basics are a plus.<\/span><\/li>\n
- Linux fundamentals, reproducible workflows.<\/span><\/li>\n<\/ul>\n
RF-Design<\/span><\/p>\n
- \n
- \n
Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.<\/p>\n<\/li>\n
- \n
Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
\u00a0<\/p>\n
Anfrage senden<\/span><\/a><\/p>\n\n\n\n\n\n\n
Contact<\/h3>\n\n\n
\r\n\r\n \r\n\r\n \r\n<\/figure> <\/div>\r\n \r\n Gianluca<\/span> Simone<\/span><\/span><\/span><\/a><\/h1>
Chair of Smart Electronics and Systems<\/span><\/p>
Research associates<\/p> \r\n <\/header>\r\n
\r\nAddress<\/h2>
Cauerstra\u00dfe 7-9<\/span> 91058<\/span> Erlangen<\/span><\/span><\/address><\/div><\/div>Contact<\/h2>
- Email: <\/span>gianluca.simone@fau.de<\/a><\/span><\/li><\/ul><\/div>
- Basics of Cadence\/ADS\/HFSS\/CST-Basics are a plus.<\/span><\/li>\n
- Circuit Simulation<\/strong>\n