We will build an end-to-end RFIC and RF packaging design flow<\/strong> The focus of this work is RF packaging and chip\u2013package\u2013PCB transitions<\/strong>, including bondwires, bond pads, package interconnects, and RF transitions to PCB or antennas<\/strong>.<\/p>\n The work includes:<\/p>\n RFIC and package-aware circuit design (schematic, layout, verification)<\/p>\n<\/li>\n Full-wave EM simulation of packaging structures<\/p>\n<\/li>\n Circuit\u2013EM co-simulation and de-embedding<\/p>\n<\/li>\n Benchmarking open-source tools against Cadence \/ ADS \/ HFSS \/ CST<\/strong><\/p>\n<\/li>\n<\/ul>\n How large are the discrepancies between open-source<\/strong> and commercial<\/strong> tools for:<\/p>\n S-parameters<\/p>\n<\/li>\n Gain, NF, P1dB, IP3<\/p>\n<\/li>\n Phase and group delay<\/p>\n<\/li>\n<\/ul>\n<\/li>\n Which effects dominate these discrepancies:<\/p>\n Packaging parasitics (bondwires, pads, transitions)<\/p>\n<\/li>\n Port definitions and de-embedding<\/p>\n<\/li>\n EM meshing and numerical settings<\/p>\n<\/li>\n Model and layout abstractions<\/p>\n<\/li>\n<\/ul>\n<\/li>\n How accurately can chip\u2013package\u2013PCB transitions<\/strong> be modeled with open-source EM solvers?<\/p>\n<\/li>\n How can the open-source RF packaging flow<\/strong> be simplified and improved:<\/p>\n Netlisting and co-simulation interfaces<\/p>\n<\/li>\n EM setup, boundary conditions, and ports<\/p>\n<\/li>\n Automation and reproducibility<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n Develop parametric packaging models<\/strong>:<\/p>\n Bondwires, pad stacks, package transitions<\/p>\n<\/li>\n<\/ul>\n<\/li>\n Automation<\/strong>:<\/p>\n Python pipelines for parameter sweeps, EM simulations, post-processing and packaging simulation<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n Skills<\/strong><\/p>\n Programmierung\/EDA<\/span><\/p>\n RF-Design<\/span><\/p>\n Fundamentals of S-parameters, matching, stability; optional: noise, large-signal, phase noise.<\/p>\n<\/li>\n Understanding of common RF topologies (amplifiers, mixers, oscillators, passive networks).<\/p>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n Anfrage senden<\/span><\/a><\/p>\n\n\n\n\n\n\n Chair of Smart Electronics and Systems<\/span><\/p> Research associates<\/p> \r\n <\/header>\r\n
(schematic \u2192 layout \u2192 EM \u2192 circuit\/EM co-simulation)<\/em> using both open-source tools<\/strong> and commercial environments<\/strong>, and systematically correlate the results<\/strong>.<\/p>\n\n
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<\/figure> <\/div>\r\n Gianluca<\/span> Simone<\/span><\/span><\/span><\/a><\/h1>
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