{"id":23908,"date":"2026-02-13T11:12:44","date_gmt":"2026-02-13T10:12:44","guid":{"rendered":"https:\/\/www.lites.tf.fau.de\/?p=23908"},"modified":"2026-02-13T11:19:21","modified_gmt":"2026-02-13T10:19:21","slug":"fp-verifikation-und-dokumentation-des-digital-design-workflows-auf-der-tiny-tapeout-plattform","status":"publish","type":"post","link":"https:\/\/www.lites.tf.fau.de\/en\/2026\/02\/13\/fp-verifikation-und-dokumentation-des-digital-design-workflows-auf-der-tiny-tapeout-plattform\/","title":{"rendered":"FP: Verification and documentation of the digital design workflow on the Tiny Tapeout platform"},"content":{"rendered":"\n<p>The&nbsp;<strong>Open Electronics Lab<\/strong>&nbsp;invites students to gain first-hand experience in the&nbsp;<strong>design and fabrication of digital integrated circuits<\/strong>&nbsp;in their spare time.<br>Thanks to the&nbsp;<strong><a rel=\"noreferrer noopener\" href=\"https:\/\/tinytapeout.com\/\" target=\"_blank\">Tiny Tapeout<\/a><\/strong>&nbsp;platform, it is now possible to realize personal digital designs using&nbsp;<strong>open-source PDKs and tools<\/strong>, all the way through to physical fabrication.<br>As part of this research internship, a&nbsp;<strong>simple digital circuit<\/strong>&nbsp;(e.g., an FSM or similar design) will be implemented from logical specification to layout and submitted for fabrication. The project will make use of the&nbsp;<strong>established open-source toolchain<\/strong>&nbsp;available at the chair.<br>In addition, the&nbsp;<strong>entire design workflow<\/strong>&nbsp;for the Tiny Tapeout platform will be documented and evaluated in terms of usability and reproducibility.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Research Questions<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>What challenges arise when implementing digital designs using open-source EDA tools?<\/li>\n\n\n\n<li>How reliable are the synthesis, place-and-route, and verification steps compared to industrial tools?<\/li>\n\n\n\n<li>Which design flows are best suited for teaching and prototyping small digital systems?<\/li>\n\n\n\n<li>Where can the Tiny Tapeout workflow be automated or optimized?<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Objectives<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Documentation of a\u00a0<strong>complete digital design workflow<\/strong>\u00a0for a Tiny Tapeout MPW run<\/li>\n\n\n\n<li>Design, simulation, synthesis, and layout of a\u00a0<strong>simple digital circuit<\/strong><\/li>\n\n\n\n<li>Evaluation of\u00a0<strong>open-source tools<\/strong>\u00a0for educational and research applications<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Work Packages<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>System &amp; Specification<\/strong>\n<ul class=\"wp-block-list\">\n<li>Definition of functionality, interfaces, and design metrics<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>RTL Design &amp; Verification<\/strong>\n<ul class=\"wp-block-list\">\n<li>Design in\u00a0<strong>Verilog\/SystemVerilog<\/strong><\/li>\n\n\n\n<li>Functional simulation using\u00a0<strong>Icarus Verilog<\/strong>,\u00a0<strong>Verilator<\/strong>, or\u00a0<strong>GTKWave<\/strong><\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Synthesis &amp; Implementation<\/strong>\n<ul class=\"wp-block-list\">\n<li>Logic synthesis with\u00a0<strong>Yosys<\/strong>, place-and-route with\u00a0<strong>OpenLane<\/strong><\/li>\n\n\n\n<li>Signoff checks (DRC\/LVS) and GDS generation<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Documentation &amp; Automation<\/strong>\n<ul class=\"wp-block-list\">\n<li>Script-based workflow (Makefile\/Python), reproducibility, and CI integration<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Your Background<\/h2>\n\n\n\n<p><em>(Not all criteria are mandatory.)<\/em><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>General:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Strong academic performance (overall grade better than\u202f2.0)<\/li>\n\n\n\n<li>Interest in digital design and open-source EDA tools<\/li>\n\n\n\n<li>Field of study: Electrical Engineering, Computer Science, or related<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Programming &amp; EDA:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Solid knowledge of\u00a0<strong>Verilog<\/strong>\u00a0or\u00a0<strong>VHDL<\/strong><\/li>\n\n\n\n<li>Experience with\u00a0<strong>Python<\/strong>\u00a0for automation and testbenching<\/li>\n\n\n\n<li>Basic experience with\u00a0<strong>Linux<\/strong>\u00a0and reproducible workflows<\/li>\n\n\n\n<li>Familiarity with\u00a0<strong>OpenLane<\/strong>,\u00a0<strong>Yosys<\/strong>,\u00a0<strong>Magic<\/strong>, or\u00a0<strong>KLayout<\/strong>\u00a0is an advantage<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Digital Design:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Understanding of digital design fundamentals (logic, FSMs, clocking, pipelines)<\/li>\n\n\n\n<li>Attendance of courses or labs such as\u00a0<strong>VHDL<\/strong>\u00a0or\u00a0<strong>Digital ASIC Design Lab<\/strong>\u00a0is beneficial<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li><strong>Practical Skills &amp; Motivation:<\/strong>\n<ul class=\"wp-block-list\">\n<li>Enthusiasm for experimenting with new tools<\/li>\n\n\n\n<li>Interest in\u00a0<strong>IC design<\/strong>,\u00a0<strong>digital verification<\/strong>, and\u00a0<strong>open-source design flows<\/strong><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n\n\n\n<div class=\"elements-divider\"><\/div>\n\n\n<a class=\"rrze-elements standard-btn primary-btn\" href=\"mailto:alexander.berwald@fau.de?subject=Anfrage%20f\u00fcr:%20FP:%20Tiny%20Tapeout%20Digital%20Workflow\"><span>Anfrage senden<\/span><\/a>\n","protected":false},"excerpt":{"rendered":"<p>The&nbsp;Open Electronics Lab&nbsp;invites students to gain first-hand experience in the&nbsp;design and fabrication of digital integrated circuits&nbsp;in their spare time.Thanks to the&nbsp;Tiny Tapeout&nbsp;platform, it is now possible to realize personal digital designs using&nbsp;open-source PDKs and tools, all the way through to physical fabrication.As part of this research internship, a&nbsp;simple digital circuit&nbsp;(e.g., an FSM or similar design) [&hellip;]<\/p>\n","protected":false},"author":4818,"featured_media":22033,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_rrze_cache":"enabled","_rrze_multilang_single_locale":"en_US","_rrze_multilang_single_source":"https:\/\/www.lites.tf.fau.de\/?p=23904","footnotes":""},"categories":[580,226],"tags":[],"workflow_usergroup":[],"class_list":["post-23908","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-fp","category-offene_stud_arbeiten_eng","en-US"],"_links":{"self":[{"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/posts\/23908","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/users\/4818"}],"replies":[{"embeddable":true,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/comments?post=23908"}],"version-history":[{"count":2,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/posts\/23908\/revisions"}],"predecessor-version":[{"id":23910,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/posts\/23908\/revisions\/23910"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/media\/22033"}],"wp:attachment":[{"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/media?parent=23908"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/categories?post=23908"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/tags?post=23908"},{"taxonomy":"workflow_usergroup","embeddable":true,"href":"https:\/\/www.lites.tf.fau.de\/wp-json\/wp\/v2\/workflow_usergroup?post=23908"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}